Changes

===== R'-packet - soft reset =====

===== R'-packet - soft reset =====

The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPGA_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partnet) as well as a debug byte and a reset mask for the on-board chips. The syntax of the debug byte has not been defined yet, but the reset mask currently the two least significant bits as reset flags for SPI bus (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage.

The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPGA_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partner) as well as a debug byte and a reset mask for the on-board chips. The syntax of the debug byte has not been defined yet, but the reset mask currently the two least significant bits as reset flags for SPI bus (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage.

 

=== The query cycle - "Q" packet ===

=== The query cycle - "Q" packet ===