Changes

===== R-packet - hard reset =====

===== R-packet - hard reset =====

The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPAG_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC) loads its own MAC address and transmits an [[Ethernet_packets#"S" packet: status report|S-packet]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).

The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPGA_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC) loads its own MAC address and transmits an [[Ethernet_packets#"S" packet: status report|S-packet]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).

===== R'-packet - soft reset =====

===== R'-packet - soft reset =====

The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPAG_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partnet) as well as a debug byte and a reset mask for the on-board chips. The syntax of the debug byte has not been defined yet, but the reset mask currently the two least significant bits as reset flags for SPI bus (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage.

The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPGA_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partnet) as well as a debug byte and a reset mask for the on-board chips. The syntax of the debug byte has not been defined yet, but the reset mask currently the two least significant bits as reset flags for SPI bus (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage.

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Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte.  All channels are present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value.  The total size of the data in a programming packet is:

Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte.  All channels are present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value.  The total size of the data in a programming packet is:

== Packets from the FPGA to the PC ==

== Packets from the FPGA to the PC ==