Changes

=== The reset cycle - "R" packets ===

=== The reset cycle - "R" packets ===

[[Image:OperationCourse.png|thumb|255px|Operation course between the digital board and the controller PC]]

[[Image:OperationCourse.png|thumb|350px|Operation course between the digital board and the controller PC]]

The reset cycle is a conversation whose purpose is to reset the digital control board.  On each power-on, the various chips on the digital board need to be re-initialized.  This includes the Ethernet chip itself, so the reset functionality needs to be built into the FPGA logic by default and needs to execute on start-up with no external stimulus in order to obtain Ethernet control.  However it may also be necessary to instigate a reset externally for some reason.  This cycle allows the external PC to initiate a reset and will notify the PC when the system is fully initialized.

The reset cycle is a conversation whose purpose is to reset the digital control board.  On each power-on, the various chips on the digital board need to be re-initialized.  This includes the Ethernet chip itself, so the reset functionality needs to be built into the FPGA logic by default and needs to execute on start-up with no external stimulus in order to obtain Ethernet control.  However it may also be necessary to instigate a reset externally for some reason.  This cycle allows the external PC to initiate a reset and will notify the PC when the system is fully initialized.