261
edits
Changes
Jump to navigation
Jump to search
Line 445:
Line 445: + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Digital control board documentation (view source)
Revision as of 18:08, 15 June 2009
, 18:08, 15 June 2009added EEPROM
| FPGA/PROG_B
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
| Used during FPGA configuration - see Xilinx documentation
|}
== EEPROM ==
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.
=== Power Details ===
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.
=== Flashing/Burning/Writing ===
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.
=== FPGA Configuration ===
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.
=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| FPGA/DIN
| Serial data line<br>Carries data from the EEPROM to the FPGA
|-
| 2
| No connection
|
|-
| 3
| FPGA/CCLK
| Configuration clock<br>Auto generated by FPGA at power-on, disabled at end of configuration
|-
| 4
| EEPROM/TDI
| This is the EEPROM's TDI<br>This is the entry point for the onboard JTAG chain
|-
| 5
| FPGA/TMS
| JTAG TMS<br>Connects to both FPGA and EEPROM
|-
| 6
| FPGA/TCK
| JTAG TCK<br>Connects to both FPGA and EEPROM
|-
| 7
| FPGA/PROG_B
| Used during configuration<br>See Xilinx documentation
|-
| 8
| FPGA/INIT_B
| Used during configuration - can be used to intiate reconfiguration of FPGA<br>See Xilinx documentation
|-
| 9
| No connection
|
|-
| 10
| FPGA/DONE
| Indicates completion of FPGA configuration<br>High when complete
|-
| 11
| DGND
|
|-
| 12-16
| No connection
|
|-
| 17
| FPGA/TDI
| This is the EEPROM's TDO/FPGA's TDI
|-
| 18-20
| +3.3V
|
|}
|}