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Digital control board documentation (view source)
Revision as of 18:35, 11 June 2009
, 18:35, 11 June 2009→Pinout Table
| P4
| P4
| SPI
| SPI
| '''Erroneously wired SPI bus trace... see notes below (coming soon)'''
| '''Erroneously wired SPI bus trace'''<br>Connects to SDO on temp. sensor and DIN on ADC
|-
|-
| P5
| P5
| CP2201/ALE
| CP2201/ALE
| Address line enable for ethernet controller
| Address line enable for ethernet controller
|-
| P45
| +3.3V
|
|-
| P46
| CP2201/RESET
| Reset pin for ethernet controller
|-
| P47
| DGND
|
|-
| P48
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
|-
| P49
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
|-
| P50
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
|-
| P51
| FPGA/DIN
| Serial data input from EEPROM for configuration
|-
| P52
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
|-
| P53
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at <br>power on to clock the configuration process)<br>See Xilinx documentation
|-
| P54
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
|-
| P55
| +3.3V
|
|-
| P56
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
|-
| P57
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
|-
| P58
| DGND
|
|-
| P59
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
|-
| P60
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
|-
| P61
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
|-
| P62
| No connection
|
|-
| P63
| DGND
|
|-
| P64
| No connection
|
|-
| P65
| No connection
|
|-
| P66
| +1.2V
|
|-
| P67
| +3.3V
|
|-
| P68
| +3.3V
|
|-
| P69
| DGND
|
|-
| P70
| ID3
| Backplane location identifier jumper, pins 3 & 4<br>Active-low, FPGA should pull high
|-
| P71
| ID2
| Backplane location identifier jumper, pins 5 & 6<br>Active-low, FPGA should pull high
|-
| P72
| ID1
| Backplane location identifier jumper, pins 7 & 8<br>Active-low, FPGA should pull high
|-
| P73
| ID0
| Backplane location identifier jumper, pins 9 & 10<br>Active-low, FPGA should pull high
|-
| P74
| DGND
|
|-
| P75
| FPGA/TDO
| JTAG
|-
| P76
| FPGA/TCK
| JTAG
|-
| P77
| ID4
| Backplane location identifier jumper, pins 1 & 2<br>Active-low, FPGA should pull high
|-
| P78
| No connection
|
|-
| P79
| +3.3V
|
|-
| P80
| DGND
|
|-
| P81
| +1.2V
|
|-
| P82
| No connection
|
|-
| P83
| CLK_5MHZ_2
| 5 MHz clock output for DAC
|-
| P84
| No connection
|
|-
| P85
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
|-
| P86
| No connection
|
|-
| P87
| DGND
|
|-
| P89
| No connection
|
|-
| P90
| No connection
|
|-
| P91
| DGND
|
|-
| P92
| +3.3V
|
|-
| P93
| AD7314/CE
| Chip enable for temperature sensor
|-
| P94
| No connection
|
|-
| P95
| DGND
|
|-
| P96
| +3.3V
|
|-
| P97
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection'''<br>Connects to DOUT on ADC
|-
| P98
| AD5535/RESET
| Reset pin for DAC
|-
| P99
| DGND
|
|-
| P100
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
|}
|}