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Digital control board documentation (view source)
Revision as of 19:12, 15 June 2009
, 19:12, 15 June 2009adding DAC
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== JTAG Header ==
To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.
===Header Location and Size===
The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.
===Power Details===
The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.
===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| Ground pins for signal integrity<br>'''Never connect a flying lead to these pins'''<br>Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
| 2
| +3.3V
| Power source for all JTAG logic
|-
| 4
| FPGA/TMS
| JTAG TMS - connects to EEPROM and FPGA
|-
| 6
| FPGA/TCK
| JTAG TCK - connects to EEPROM and FPGA
|-
| 8
| FPGA/TDO
| JTAG boundary scan chain endpoint
|-
| 10
| EEPROM/TDI
| JTAG boundary scan chain start point
|-
| 12
| No connection
| Pin is floating
|-
| 14
| No connection
| Pin is floating
|}
===JTAG Overview===
The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.
The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.
The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.
== DAC ==
The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.
=== Power Details ===
The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in [[#Power Requirements]]. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.
It should be noted that the DAC is designed to be able to output up to 200V on any or all of its channels, and to source up to 700uA per channel regardless of the voltage being output. However, there is no reason why the high voltage line can't be set to a lower voltage if 200V is not needed.
=== Thermal Diode ===
The DAC has a built in thermal diode. The diode drop from anode to cathode is 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC).
=== Pinout Table ===
See documentation from Analog Devices.
=== Channel Mapping ===
Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''