Changes

== (00X) Reset Modules ==

= (00X) Reset Modules =

The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved)

The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved)

The control packets leading to states 00X pertaining to thes reset modules are:

The control packets type bytes leading to states 00X pertaining to these reset modules are:

{|

{| class="wikitable" border="1" align="center" style="text-align:center" cellspacing="0" cellpadding="4"

! Packet Type Byte || Hex value || Bin value || Description

! colspan="3" | Packet Type Byte || colspan="2" | Effect on the FPGA

|-

|-

| R || 0x52 || 0101 0010

! Type || Hex || Bin || State || Description

|-

|-

| "R'" || 0xD2 || '''1'''101 0010

| "R'" || 0xD2 || '''1'''101 0010 || 001 || align="left" | Essentially an 'R' byte with '1' in the MSB instructing the FPGA to enter a reset cycle of the soft kind.

|}

|}

* ''Clk'': [in] clock

* ''Clk'': [in] clock