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FPGA Reset
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Revision as of 18:50, 29 May 2008
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18:50, 29 May 2008
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Line 5:
Line 5:
The control packets leading to states 00X pertaining to thes reset modules are:
The control packets leading to states 00X pertaining to thes reset modules are:
{|
{|
−
|+
Packet Type Byte || Hex value || Bin value || Description
+
!
Packet Type Byte || Hex value || Bin value || Description
+
|-
| R || 0x52 || 0101 0010
| R || 0x52 || 0101 0010
|-
|-
Senderovich
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