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FPGA Reset
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Revision as of 20:37, 30 May 2008
1 byte removed
,
20:37, 30 May 2008
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Line 44:
* ''TxRx_Aout'': [out] EC control register address (8-bit)
* ''TxRx_Aout'': [out] EC control register address (8-bit)
* ''TxRx_Dout'': [out] EC control register write value
* ''TxRx_Dout'': [out] EC control register write value
−
* ''TxRx_RiW'': [out]
active-high read, active-low write flag
+
* ''TxRx_RiW'': [out] active-high read, active-low write flag
* ''TxRx_Din'': [in] EC control register return value
* ''TxRx_Din'': [in] EC control register return value
* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]].
* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]].
* ''dbShort'': [in] debug signal to bypass EC reset waiting periods
* ''dbShort'': [in] debug signal to bypass EC reset waiting periods
Senderovich
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