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Programming the Ethernet controller (view source)
Revision as of 18:20, 19 May 2008
, 18:20, 19 May 2008→State-Module organization
The core of the the FPGA is divided roughly into eight modules enabled by by the 3-bit state value. Below is an index of the states and their corresponding modules. In this discussion of states, 'X' is a binary wild card the values are immediately explained.
The core of the the FPGA is divided roughly into eight modules enabled by by the 3-bit state value. Below is an index of the states and their corresponding modules. In this discussion of states, 'X' is a binary wild card the values are immediately explained.
{| class="wikitable" border="1" cellspacing="0" cellpadding="4"
{| class="wikitable" border="1" align="center" style="text-align:center" cellspacing="0" cellpadding="4"
|+ State-Module Index
|+ State-Module Index
|- align="center"
|-
! State !! Module Name !! Description !! Succeeding State
! State !! Module Name !! Description !! Succeeding State
|-
|-
| align="center" | 000 || [[FPGA_Reset|Reset]]_hard || Coordinates the reset and start-up of the EC. || 101
| align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 101
|-
|-
| align="center" | 001 || [[FPGA_Reset|Reset]]_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
| align="center" | 001 || [[FPGA_Reset|Reset]]_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101