Changes

| align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 101

| align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 101

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| align="center" | 001 || [[FPGA_Reset|Reset]]_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101

| align="center" | 001 || [[FPGA_Reset|Reset]]_soft || align="left" | Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101

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| align="center" | 010 || [[FPGA_Idler|Idler]] || This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011

| align="center" | 010 || [[FPGA_Idler|Idler]] || align="left" | This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011

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| align="center" | 011 || [Packet] [[FPGA_Reader|Reader]] || Skips the packet header and reads the first two bytes ("location" and "type") of the packet payload. It rejects misdirected or invalid-type bytes. Control is passed according to packet type to Query, Program or Reset Modules || 100, 110, 00X

| align="center" | 011 || [Packet] [[FPGA_Reader|Reader]] || align="left" | Skips the packet header and reads the first two bytes ("location" and "type") of the packet payload. It rejects misdirected or invalid-type bytes. Control is passed according to packet type to Query, Program or Reset Modules || 100, 110, 00X

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| align="center" | 100 || [[FPGA_Querier|Querier]] || Queries the values of the Temperature sensor and ADC, stores them in their respective registers and passes control to the Transmitter for delivery || 101   

| align="center" | 100 || [[FPGA_Querier|Querier]] || align="left" | Queries the values of the Temperature sensor and ADC, stores them in their respective registers and passes control to the Transmitter for delivery || 101   

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| align="center" | 110 || [DAC] [[FPGA_Programmer|Programmer]] || Programs the DAC based on instructions in packet and stores the values in the DAC register. || 111

| align="center" | 110 || [DAC] [[FPGA_Programmer|Programmer]] || align="left" | Programs the DAC based on instructions in packet and stores the values in the DAC register. || 111

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| align="center" | 1X1 || [Packet] [[FPGA_Transmitter|Transmitter]] || Composes and sends a packet of either [[Ethernet_packets|'S' or 'D' type]]. These correspond respectively to "'''S'''tatus" values reported by the sensor chips (state=101) and current '''D'''AC values (state=111) || 010

| align="center" | 1X1 || [Packet] [[FPGA_Transmitter|Transmitter]] || align="left" | Composes and sends a packet of either [[Ethernet_packets|'S' or 'D' type]]. These correspond respectively to "'''S'''tatus" values reported by the sensor chips (state=101) and current '''D'''AC values (state=111) || 010

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