Changes

== Foreword on Timing ==

== Foreword on Timing ==

With a controller this complex, the timing of signals must be inspected even more scrupulously than usual. In particular, simultaneous transitions of data and "Done" lines must be avoided. This is solved by either

With a controller this complex, the timing of signals must be inspected even more scrupulously than usual. Simultaneity of the rising edge of the "Done" signal and the corresponding output data may not be guaranteed. This is solved by either

# a one-cycle-delayed "Done" signal to ensure that the data lines have been stabilized. (All delays are implemented via the <tt>c_delay</tt> module which postpones the signal by one cycle via two sequential flip-flops, each shifting by half-cycle).   

# a one-cycle-delayed "Done" signal to ensure that the data lines have been stabilized. (All delays are implemented via the <tt>c_delay</tt> module which postpones the signal by one cycle via two sequential flip-flops, each shifting by half-cycle).   

# coding the target component to read the data lines on the ''falling edge'' of the clock during the a "Go" signal.  

# coding the target component to read the data lines on the ''falling edge'' of the clock during the a "Go" signal.  

The latter method turned out to be the dominant one in this design.

The latter method turned out to be the dominant one in this design.

== The eight states ==

== The eight states ==