Changes

| 000 || [[FPGA_Reset|Reset]]_hard || Coordinates the reset and start-up of the Ethernet Controller chip. || 101

| 000 || [[FPGA_Reset|Reset]]_hard || Coordinates the reset and start-up of the Ethernet Controller chip. || 101

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| 001 || [[FPGA_Reset|Reset Modules]]_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101

| 001 || [[FPGA_Reset|Reset]]_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101

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| 010 || [[FPGA_Idler|Idler]] || This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011

| 010 || [[FPGA_Idler|Idler]] || This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011