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mLine 31:
Line 31: − + − + − + − + − + + + + + − | 110 || Programmer || Programs the DAC based on instructions in packet and stores the values in the DAC register. Line 92:
Line 95: − [[FPGA_Reset|Reset Modules]] − [[FPGA_Idler|Idler (Idle Process Module)]] − [[FPGA_Reader|Packet Reader]] (Packet type inspection) − [[FPGA_Querier|Querier (status query module)]] − [[FPGA_Programmer|DAC Programmer]]+ + + + + + − [[FPGA_Transmitter|Packet Transmitter]]
Programming the Ethernet controller (view source)
Revision as of 17:41, 19 May 2008
, 17:41, 19 May 2008no edit summary
! State !! Module Name !! Description !! Succeeding State
! State !! Module Name !! Description !! Succeeding State
|-
|-
| 000 || Reset_hard || Coordinates the reset and start-up of the Ethernet Controller chip. || 101
| 000 || [[FPGA_Reset|Reset]]_hard || Coordinates the reset and start-up of the Ethernet Controller chip. || 101
|-
|-
| 001 || Reset_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
| 001 || [[FPGA_Reset|Reset Modules]]_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
|-
|-
| 010 || Idler || This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011\
| 010 || [[FPGA_Idler|Idler]] || This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011
|-
|-
| 011 || Reader || Skips the packet header and reads the first two bytes ("location" and "type") of the packet payload. It rejects misdirected or invalid-type bytes. Control is passed according to packet type to Query, Program or Reset Modules || 100, 110, 000, 001
| 011 || Packet [[FPGA_Reader|Reader]] || Skips the packet header and reads the first two bytes ("location" and "type") of the packet payload. It rejects misdirected or invalid-type bytes. Control is passed according to packet type to Query, Program or Reset Modules || 100, 110, 00X
|-
|-
| 100 || Querier || Queries the values of the Temperature sensor and ADC, stores them in their respective registers and passes control to the Transmitter for delivery || 101
| 100 || [[FPGA_Querier|Querier]] || Queries the values of the Temperature sensor and ADC, stores them in their respective registers and passes control to the Transmitter for delivery || 101
|-
| 110 || DAC [[FPGA_Programmer|Programmer]] || Programs the DAC based on instructions in packet and stores the values in the DAC register. || 111
|-
| 1X1 || Packet [[FPGA_Transmitter|Transmitter]] || Composes and sends a packet of either 'S' or 'D' type. These correspond respectively to "'''S'''tatus" values reported by the sensor chips (state=101) and current '''D'''AC values (state=111) || 010
|-
|-
|}
|}
[[FPGA_Transceiver|Transceiver]]
[[FPGA_Transceiver|Transceiver]]
(Packet type inspection)
(status query module)]]