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Line 6: − + − − = Interface = − − :''See also: [[Ethernet packets]]'' − − [[Image:MuxIntelTiming.png|frame|Multiplexed Intel Bus and internal I/O timing scheme enforced by FPGA clocks]] − − The compact approach to wire and poll the Ethernet Controller chop is via the Multiplexed Intel bus format. Aside from some use of the interrupt and reset pins, all communication is done via this bus. (The control architecture of the chip uses 8-bit registers selected with 8-bit addresses.) A communication over this bus begins with an pulse on the "ALE" pin, by the fall of which a valid address is expected on the 8-bit inout "AD" bus. After this /RD (/WR) signal falls, executing the read (write) process, and then rises accompanied with valid input from (to) the chip. The adjacent figure illustrates this process along with the approach to timing the conversation taken in this design. Please refer to Section 16.2 in the manual for details on the timing tolerances on this bus. − − As shown in the figure, the 20 MHz clock is very convenient for metering this conversation. The communication delay for the FPGA (most of which runs essentially on 5 MHz) turns out to be only two clock cycles. − There are eight major states to the module.+ − − == State list == Line 31:
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Programming the Ethernet controller (view source)
Revision as of 17:59, 19 May 2008
, 17:59, 19 May 2008no edit summary
The modules involved in communication with the Ethernet Controller chip serve as the core of the FPGA. The different tasks that need to be performed by these modules include
The modules involved in communication with the Ethernet Controller chip (EC) serve as the core of the FPGA. The different tasks that need to be performed by these modules include
* executing the complex board reset and address lookup sequence
* executing the complex board reset and address lookup sequence
* polling for new packets and switching execution accordingly
* polling for new packets and switching execution accordingly
* building return packets
* building return packets
In our design, the modules involved with packet handling and interfacing with sensor chip controllers are organized by ''state''. A state register specifies the current stage of the process and only the corresponding module is allowed to act during that stage. Aside from defining a process sequence, the state serves as a complex "enable" signal for the modules, ensuring that only one module is driving the communication bus used to query the Ethernet Controller chip.
In our design, the modules involved with packet handling and interfacing with sensor chip controllers are organized by ''state''. A state register specifies the current stage of the process and only the corresponding module is allowed to act during that stage. Aside from defining a process sequence, the state serves as a complex "enable" signal for the modules, ensuring that only one module is driving the communication bus used to query the EC.
= The eight states =
= The eight states =
The core of the the FPGA is divided roughly into eight modules enabled by by the 3-bit state value. Below is an index of the states and their corresponding modules. In this discussion of states, 'X' is a binary wild card the values are immediately explained.
{| class="wikitable" align="center" style="text-align:center" border="1" cellspacing="0" cellpadding="4"
{| class="wikitable" align="center" style="text-align:center" border="1" cellspacing="0" cellpadding="4"
! State !! Module Name !! Description !! Succeeding State
! State !! Module Name !! Description !! Succeeding State
|-
|-
| 000 || [[FPGA_Reset|Reset]]_hard || Coordinates the reset and start-up of the Ethernet Controller chip. || 101
| 000 || [[FPGA_Reset|Reset]]_hard || Coordinates the reset and start-up of the EC. || 101
|-
|-
| 001 || [[FPGA_Reset|Reset]]_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
| 001 || [[FPGA_Reset|Reset]]_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
| 110 || DAC [[FPGA_Programmer|Programmer]] || Programs the DAC based on instructions in packet and stores the values in the DAC register. || 111
| 110 || DAC [[FPGA_Programmer|Programmer]] || Programs the DAC based on instructions in packet and stores the values in the DAC register. || 111
|-
|-
| 1X1 || Packet [[FPGA_Transmitter|Transmitter]] || Composes and sends a packet of either 'S' or 'D' type. These correspond respectively to "'''S'''tatus" values reported by the sensor chips (state=101) and current '''D'''AC values (state=111) || 010
| 1X1 || Packet [[FPGA_Transmitter|Transmitter]] || Composes and sends a packet of either [[Ethernet_packets|'S' or 'D' type]]. These correspond respectively to "'''S'''tatus" values reported by the sensor chips (state=101) and current '''D'''AC values (state=111) || 010
|-
|-
|}
|}
= Interface =
[[Image:MuxIntelTiming.png|frame|Multiplexed Intel Bus and internal I/O timing scheme enforced by FPGA clocks]]
The compact approach to wire and poll the EC is via the Multiplexed Intel bus format. Aside from some use of the interrupt and reset pins, all communication is done via this bus. (The control architecture of the chip uses 8-bit registers selected with 8-bit addresses.) A communication over this bus begins with an pulse on the "ALE" pin, by the fall of which a valid address is expected on the 8-bit inout "AD" bus. After this /RD (/WR) signal falls, executing the read (write) process, and then rises accompanied with valid input from (to) the chip. The adjacent figure illustrates this process along with the approach to timing the conversation taken in this design. Please refer to Section 16.2 in the manual for details on the timing tolerances on this bus.
As shown in the figure, the 20 MHz clock is very convenient for metering this conversation. The communication delay for the FPGA (most of which runs essentially on 5 MHz) turns out to be only two clock cycles.
This communication standard calls for a bridge module that communicates with the EC upon request from other modules. A "[[FPGA_Transceiver|Transceiver]]" was designed for this purpose. It abstracts the communication with the EC as well as the clock frequency difference. This module in fact subdivides the main 20 MHz; clock to generate the "slow" 5 MHz clock for the rest of the FPGA. Please refer to the [[FPGA_Transceiver|detailed page]] on the Transceiver for more information.