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Programming the Ethernet controller (view source)
Revision as of 22:16, 16 May 2008
, 22:16, 16 May 2008→State list
|+ State-Module Index
|+ State-Module Index
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! State !! Function !! Module Name !! Description !! Succeeding State
! State !! Module Name !! Description !! Succeeding State
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| 000 || Hard Reset || Reset_hard || Coordinates the reset and start-up of the Ethernet Controller chip. || 101
| 000 || Reset_hard || Coordinates the reset and start-up of the Ethernet Controller chip. || 101
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| 001 || Soft Reset || Reset_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
| 001 || Reset_soft || Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
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| 010 || Idler || This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011\
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| 011 || Reader || Skips the packet header and reads the first two bytes ("location" and "type") of the packet payload. It rejects misdirected or invalid-type bytes. Control is passed according to packet type to Query, Program or Reset Modules || 100, 110, 000, 001
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| 100 || Querier || Queries the values of the Temperature sensor and ADC, stores them in their respective registers and passes control to the Transmitter for delivery || 101
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| 110 || Programmer || Programs the DAC based on instructions in packet and stores the values in the DAC register.
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