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* Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component.
* Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component.
* Do the parts work on falling or rising edges of the clock? Most VHDL designs are currently on rising edges, but this can be easily corrected.
* Do the parts work on falling or rising edges of the clock? Most VHDL designs are currently on rising edges, but this can be easily corrected.
* The temperature sensor and the ADC share the same SPI-like bus lines; can they be combined into a single VHDL design?
== The DAC ==
== The DAC ==