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* A(4:0) is a 5-bit address to select the target DAC channel. A4 is the most-significant bit and transfers first.
* A(4:0) is a 5-bit address to select the target DAC channel. A4 is the most-significant bit and transfers first.
* DB(13:0) is a 14-bit voltage code, where <math>V_{out} = 50*V_{RefIn}*\frac{DB(13:0)}{2^{14}}</math>.
* DB(13:0) is a 14-bit voltage code, where <math>V_{out} = 50*V_{RefIn}*\frac{DB(13:0)}{2^{14}}</math>.
** DB = 0 yields <math>V_{out} = 0</math>.
** DB = 0 yields V<sub>out</sub> = 0.
** DB = <math>2^{14}-1</math> (full scale) yields <math>V_{out} = 49.9969*V_{RefIn}</math>.
** DB = 2<sup>14</sup>-1 (full scale) yields V<sub>out</sub> = 49.9969*V<sub>Ref In</sub>.
The three lines of the interface are ''SYNC'', ''SCLK'', and ''D_in''. A write to the DAC begins with a falling edge of ''SYNC''. The next 19 bits (counted off by ''SCLK'') are saved into a shift register The next transfer begins on another falling edge of ''SYNC'', but transfers do not overlap or interrupt. A minimum of 200ns is required between exchanges. ''SCLK'' is ignored except during the 19 shift cycles. The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically. In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz. For further details on timing and protocol, see the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html AD5535 data sheet] supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).
The three lines of the interface are ''SYNC'', ''SCLK'', and ''D_in''. A write to the DAC begins with a falling edge of ''SYNC''. The next 19 bits (counted off by ''SCLK'') are saved into a shift register The next transfer begins on another falling edge of ''SYNC'', but transfers do not overlap or interrupt. A minimum of 200ns is required between exchanges. ''SCLK'' is ignored except during the 19 shift cycles. The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically. In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz. For further details on timing and protocol, see the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html AD5535 data sheet] supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).