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no edit summary
** inputs
** inputs
*** ''CLK'': clock
*** ''CLK'': clock
*** ''Reset'': asynchronous, active-low reset
*** ''Rst'': asynchronous, active-low reset
*** ''En'': shift enable
*** ''En'': shift enable
*** ''D'': data in line
*** ''D'': data in line
** inputs
** inputs
*** ''CLK'': clock
*** ''CLK'': clock
*** ''Reset'': asynchronous, active-low reset
*** ''Rst'': asynchronous, active-low reset
*** ''En'': read enable
*** ''En'': read enable
*** ''D'': data in
*** ''D'': data in
** inputs
** inputs
*** ''CLK'': clock
*** ''CLK'': clock
*** ''Reset'': asynchronous, active-low reset
*** ''Rst'': asynchronous, active-low reset
*** ''Sh/Ld'': shift/load toggle; active-high shift enable, active-low load enable
*** ''Sh/Ld'': shift/load toggle; active-high shift enable, active-low load enable
*** ''D'': data in
*** ''D'': data in
=== Controller (A) ===
=== Controller (A) ===
[[Image:ADC Controller Block.JPG|thumb|ADC controller functional block diagram]]
The functional block diagram for the controller is shown to the right. The blocks are:
* '''counter'''
** This block is a 5-bit counter. It counts out 17 cycles: from the idle state, a pulse on the Go line begins a count of 16 cycles (during which time CS is low), then on the 17th cycle re-enters the idle state to await another pulse on Go. The Go line is ignored during a 17-cycle run.
** inputs
*** ''CLK'': clock
*** ''Rst'': asynchronous, active-low reset
*** ''Go'': pulse to leave idle state
** outputs
*** ''CS'': active-low chip select
* '''delayer'''
** This block is a single-cycle signal delayer.
** inputs
*** ''CLK'': clock
*** ''D'': signal to be delayed
** outputs
*** ''Q'': delayed signal
* '''shift out 12'''
** This block is a 12-bit shift-out register with asynchronous, active-low reset and a shift/load toggle. Custom inputs load the write bit and address bits, then fill in the remaining bits (W00AAA110000). The register drags a trailing zero. The output idles at zero when output is not enabled.
** inputs
*** ''CLK'': clock
*** ''Rst'': asynchronous, active-low reset
*** ''Sh/Ld'': shift/load toggle; active-high shift enable, active-low load enable
*** ''D_W'': write bit input
*** ''D_A'': address bits input
** outputs
*** ''Q'': serial output
* '''shift in 15'''
** This block is a 15-bit shift-in register with asynchronous, active-low reset and shift enable. Custom outputs select the address bits and data bits.
** inputs
*** ''CLK'': clock
*** ''Rst'': asynchronous, active-low reset
*** ''Sh'': shift enable
*** ''D'': data in
** outputs
*** ''A'': address out
*** ''Q'': data out
== Ethernet controller ==
== Ethernet controller ==