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*** ''Q_W'': the write bit from the input string
*** ''Q_W'': the write bit from the input string
*** ''Q_D'': the 11 data bits from the input string
*** ''Q_D'': the 11 data bits from the input string
* '''control reg'''
** This block is an 11-bit register with asynchronous, active-low reset and a clock enable line.
** inputs
*** ''CLK'': clock
*** ''Reset'': asynchronous, active-low reset
*** ''En'': read enable
*** ''D'': data in
** outputs
*** ''Q'': data out
* '''3-to-8 demux'''
** This block is a 3-to-8 demultiplexer.
** inputs
*** ''D'': data to be demuxed
*** ''S'': 3-bit select
** outputs
*** ''Q'': 8-bit output
* '''error flag'''
** This block generates a flag to ensure that data in the control register is in the right format (to help verify synchronization). The format is: d00ddd110000, where a "d" is a don't-care state (0 or 1).
** inputs
*** ''D'': data in
** outputs
*** ''Err'': active-high error flag
* '''shift out 15'''
** This block is a 15-bit shift-out register with asynchronous, active-low reset and a shift/load toggle. Custom inputs load the address (MSB first) as the first 3 bits and the data as the last 12 bits. Idle output is a zero.
** inputs
*** ''CLK'': clock
*** ''Reset'': asynchronous, active-low reset
*** ''Sh/Ld'': shift/load toggle; active-high shift enable, active-low load enable
*** ''D'': data in
*** ''A'': address in
** outputs
*** ''Q'': data out
=== Controller (A) ===
=== Controller (A) ===