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[[Image:ADC Emulator Block.JPG|thumb|ADC emulator functional block diagram]]
[[Image:ADC Emulator Block.JPG|thumb|ADC emulator functional block diagram]]
The functional block diagram for the emulator is shown to the right. The blocks are:
* '''shift in 16'''
** This block is a 16-bit shift-in register with asynchronous, active-low reset and shift enable. Custom outputs select the write bit and the data bits from the input string. This register is designed to shift all 16 cycles of a transfer, but only make use of the first 12 bits of the input.
** inputs
*** ''CLK'': clock
*** ''Reset'': asynchronous, active-low reset
*** ''En'': shift enable
*** ''D'': data in line
** outputs
*** ''Q_W'': the write bit from the input string
*** ''Q_D'': the 11 data bits from the input string
=== Controller (A) ===
=== Controller (A) ===