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| style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | A<sub>2</sub> || style="width:15px" | A<sub>1</sub> || style="width:15px" | A<sub>0</sub> || style="width:15px" | 1 || style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | 0 || style="width:15px" | 0
| style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | A<sub>2</sub> || style="width:15px" | A<sub>1</sub> || style="width:15px" | A<sub>0</sub> || style="width:15px" | 1 || style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | 0 || style="width:15px" | 0
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where an X is a don't-care state.
where an X is a don't-care state. Since the first case is almost all don't-care states, we can send the same data (last 11 bits) as in the second case, but append a zero to the front instead of a 1; this simplifies the logic involved. The don't-care states in bits 9 and 2 we can set to zero.
The control interface to the FPGA core will be:
The control interface to the FPGA core will be: