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where an X is a don't-care state. Since the first case is almost all don't-care states, we can send the same data (last 11 bits) as in the second case, but append a zero to the front instead of a 1; this simplifies the logic involved. The don't-care states in bits 9 and 2 we can set to zero.
where an X is a don't-care state. Since the first case is almost all don't-care states, we can send the same data (last 11 bits) as in the second case, but append a zero to the front instead of a 1; this simplifies the logic involved. The don't-care states in bits 9 and 2 we can set to zero.
The data flowing back to the FPGA from the ADC will be voltage data from the channel set in the previous conversation. We are going to use twos-complement format for the data, but it can be set to BCD by changing the last bit in the control register to a one.
The control interface to the FPGA core will be:
The control interface to the FPGA core will be: