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Line 230:
Line 230: + + + + + + + + +
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| style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | A<sub>2</sub> || style="width:15px" | A<sub>1</sub> || style="width:15px" | A<sub>0</sub> || style="width:15px" | 1 || style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | 0 || style="width:15px" | 0
| style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | A<sub>2</sub> || style="width:15px" | A<sub>1</sub> || style="width:15px" | A<sub>0</sub> || style="width:15px" | 1 || style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | 0 || style="width:15px" | 0
|}
|}
where an X is a don't-care state.
The control interface to the FPGA core will be:
* ''Clk'': input: Clock line
* ''Go'': input: Pulse to begin transmission
* ''Wr'': input: Flag whether or not to write new data to control register
* ''A(2:0)'': input: Address to write to control register
* ''C(2:0)'': output: Address of data coming from ADC
* ''D(11:0)'': output: Data from ADC
=== Emulator (A) ===
=== Emulator (A) ===