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mLine 189:
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SiPM digital control board netlist (view source)
Revision as of 16:47, 24 June 2008
, 16:47, 24 June 2008→Configuration Pins: fixed naming convention for M[2:0]
|Clock for programming
|Clock for programming
|FPGA programmer?
|FPGA programmer?
|If M0-M2 define a master mode, CCLK is internally generated<br>If M0-M2 define a slave mode, CCLK is a clock input
|If M[2:0] define a master mode, CCLK is internally generated<br>If M[2:0] define a slave mode, CCLK is a clock input
|----
|----
|INIT_B
|INIT_B