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SiPM digital control board netlist
(view source)
Revision as of 16:47, 24 June 2008
2 bytes added
,
16:47, 24 June 2008
m
→Configuration Pins
:
fixed naming convention for M[2:0]
Line 189:
Line 189:
|Clock for programming
|Clock for programming
|FPGA programmer?
|FPGA programmer?
−
|If
M0-M2
define a master mode, CCLK is internally generated<br>If
M0-M2
define a slave mode, CCLK is a clock input
+
|If
M[2:0]
define a master mode, CCLK is internally generated<br>If
M[2:0]
define a slave mode, CCLK is a clock input
|----
|----
|INIT_B
|INIT_B
Underwood
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