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[[FPGA_Register#State_Register|State Register]] Control Lines
[[FPGA_Registers#State_Register|State Register]] Control Lines
* ''state_En'': [out] state register enable (write) signal
* ''state_En'': [out] state register enable (write) signal
* ''state_D'': [out] (3-bit) state register input
* ''state_D'': [out] (3-bit) state register input