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== (000) Reset Cycle ==
== (00X) Reset Modules ==
Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet Controller (EC), and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].
The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved)
Block 000 will have four functional blocks: one each for the DAC, ADC, and , and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].
MAC Address Register Control Lines
[[FPGA_Registers#MAC_Register|MAC Address Register]] Control Lines
* ''MACregs_En'': [out] register enable (write) signal
* ''MACregs_En'': [out] register enable (write) signal
* ''MACregs_A'': [out] byte address (4-bit)
* ''MACregs_A'': [out] byte address (4-bit)