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Line 1: − + − inputs − * ''Clk'': clock − * ''/Rst'': asynchronous, active-low reset − * ''State'': 3-bit state value − * ''D_En'': DAC enable, assume held high/low by previous block − * ''A_En'': ADC enable, assume held high/low by previous block − * ''E_En'': Ethernet enable, assume held high/low by previous block − internal signals+ − − * ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle − * ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En'' − * ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En'' − * ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En'' − blocks+ − * '''DAC Reset'''+ − ** Resets and initializes the DAC.+ − ** inputs+ − *** ''Clk'': clock+ − *** ''/Rst'': asynchronous, active-low reset+ − *** ''D_Go'': go pulse to begin reset/initialization process+ − ** outputs+ − *** - All DAC reset/initialization control lines -+ − *** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse+ − * '''ADC Reset'''+ − ** Resets and initializes the ADC.+ − ** inputs+ − *** ''Clk'': clock+ − *** ''/Rst'': asynchronous, active-low reset+ − *** ''A_Go'': go pulse to begin reset/initialization process+ − ** outputs+ − *** - All ADC reset/initialization control lines -+ − *** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse+ − * '''Ethernet Reset'''+ − ** Resets and initializes the Ethernet controller.+ − ** inputs+ − *** ''Clk'': clock+ − *** ''/Rst'': asynchronous, active-low reset+ − *** ''E_Go'': go pulse to begin reset/initialization process+ − ** outputs+ − *** - All Ethernet reset/initialization control lines -+ − *** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse+ − − ** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete. − ** inputs − *** ''Clk'': clock − *** ''/Rst'': asynchronous, active-low reset − *** ''D_En'': high when DAC is to be reset − *** ''D_Done'': high when DAC is done resetting − *** ''A_En'': high when ADC is to be reset − *** ''A_Done'': high when ADC is done resetting − *** ''E_En'': high when Ethernet controller is to be reset − *** ''E_Done'': high when Ethernet controller is done resetting − ** internal signals − *** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'') − ** outputs − *** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable − *** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high
no edit summary
== (000) Reset Cycle ==
== (000) Reset Cycle ==
Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].
Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet Controller (EC), and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].
* ''Clk'': [in] clock
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
Reset Signals
* ''Rst: [in] asynchronous reset
* ''Eth_iRst'': [inout] EC active-low reset pin
* ''Eth_iINT'': [in] EC active-low interrupt signal
[[FPGA_Register#State_Register|State Register]] Control Lines
* ''state_En'': [out] state register enable (write) signal
* ''state_D'': [out] (3-bit) state register input
* ''state_Q'': [in] (3-bit) state register output
MAC Address Register Control Lines
* ''MACregs_En'': [out] register enable (write) signal
* ''MACregs_A'': [out] byte address (4-bit)
* ''MACregs_D'': [out] 8-bit input value
[[FPGA_Transceiver|Transceiver]] Control Lines
* ''TxRx_Go'': [out] "Go" signal to read/write an EC control register byte
* ''TxRx_Aout'': [out] EC control register address (8-bit)
* ''TxRx_Dout'': [out] EC control register write value
* ''TxRx_RiW'': [out] active-high read, active-low write flag
* ''TxRx_Din'': [in] EC control register return value
* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]].
* ''dbShort'': [in] debug signal to bypass EC reset waiting periods
* '''Coordinator'''