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Programming the Ethernet controller (view source)
Revision as of 06:33, 5 November 2009
, 06:33, 5 November 2009→State-Module organization
| align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 100
| align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 100
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|-
| align="center" | 001 || [[FPGA_Reset|Reset]]_soft || align="left" | Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
| align="center" | 001 || [[FPGA_Reset|Reset]]_soft || align="left" | Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 100
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|-
| align="center" | 010 || [[FPGA_Idler|Idler]] || align="left" | This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011
| align="center" | 010 || [[FPGA_Idler|Idler]] || align="left" | This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011
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|}
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=== State interconnect ===
=== State interconnect ===