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=== State interconnect ===

=== State interconnect ===

This communication standard calls for a bridge module that communicates with the EC upon request from other modules. A "[[FPGA_Transceiver|Transceiver]]" was designed for this purpose. It abstracts the communication with the EC as well as the clock frequency difference. This module in fact subdivides the main 20 MHz; clock to generate the "slow" 5 MHz clock for the rest of the FPGA. Please refer to the [[FPGA_Transceiver|detailed page]] on the Transceiver for more information.

This communication standard calls for a bridge module that communicates with the EC upon request from other modules. A "[[FPGA_Transceiver|Transceiver]]" was designed for this purpose. It abstracts the communication with the EC as well as the clock frequency difference. This module in fact subdivides the main 20 MHz; clock to generate the "slow" 5 MHz clock for the rest of the FPGA. Please refer to the [[FPGA_Transceiver|detailed page]] on the Transceiver for more information.

== Combined control flow ==

== Combined control flow ==

[[Image:DigBoardScheme.png|center]]

[[Image:DigBoardScheme.png|center]]

= Emulator =

= Emulator =

* Non-state Modules

* Non-state Modules

** [[FPGA_Transceiver|Transceiver]]

** [[FPGA_Transceiver|Transceiver]]

** [[FPGA_Registers|Registers]]

** [[FPGA_Registers|Registers]]

* [[Ethernet_packets|Ethernet Packet formatting]]

* [[Ethernet_packets|Ethernet Packet formatting]]