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Line 33: − ===== R-packet - hard reset =====+ − ===== R'-packet - soft reset =====+ + + − The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPGA_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partner) as well as a reset mask for the on-board chips. Currently the two least significant bits of this byte order reset of the ADC bus (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage. Line 69:
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=== Transmitting ===
=== Transmitting ===
To the right is a diagram depicting the structure of an Ethernet packet. On the left side is marked the blocks that must be defined by the FPGA to be passed to the CP2200/1. The first 8 bytes ("Preamble and Start Frame Delimiter") and last 4 bytes ("CRC") will be generated by the CP2200/1, so the FPGA need not even be aware of them. The first significant block is the 6-byte destination MAC address. The FPGA will have to store this to know the address of its conversation partnet. The next block is the 6-byte source MAC address. Each CP2200/1 comes with a factory-set unique MAC address stored in the last page of Flash memory that will be used as the source MAC address. This address must be retrieved at startup, insterted in the MAC interface of the CP2200/1 as well as stored by the FPGA for packet addressing. The next block is the 2-byte length block. This is the number of bytes of data, i.e. everything between the length block and the CRC. Then finally comes the data block, which must be padded to a minimum of 46 bytes but cannot exceed 1,500 bytes. In practice, out packets are padded to 47 bytes of payload: ''the letter'' of the CP2200/1 manual seems to indicate although this is likely a mistake. (Their likely error reduces to the fact that N-member array with first index 0 ends with index N-1, not N.)
To the right is a diagram depicting the structure of an Ethernet packet. On the left side is marked the blocks that must be defined by the FPGA to be passed to the CP2200/1. The first 8 bytes ("Preamble and Start Frame Delimiter") and last 4 bytes ("CRC") will be generated by the CP2200/1, so the FPGA need not even be aware of them. The first significant block is the 6-byte destination MAC address. The FPGA will have to store this to know the address of its conversation partnet. The next block is the 6-byte source MAC address. Each CP2200/1 comes with a factory-set unique MAC address stored in the last page of Flash memory that will be used as the source MAC address. This address must be retrieved at start-up, inserted in the MAC interface of the CP2200/1 as well as stored by the FPGA for packet addressing. The next block is the 2-byte length block. This is the number of bytes of data, i.e. everything between the length block and the CRC. Then finally comes the data block, which must be padded to a minimum of 46 bytes but cannot exceed 1,500 bytes. In practice, out packets are padded to 47 bytes of payload: ''the letter'' of the CP2200/1 manual seems to indicate although this is likely a mistake. (Their likely error reduces to the fact that N-member array with first index 0 ends with index N-1, not N.)
==== R-packet - hard reset ====
The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPGA_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC), loads its own MAC address and transmits an [[Ethernet_packets#"S" packet: status report|S-packet]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).
The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPGA_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC), loads its own MAC address and transmits an [[Ethernet_packets#"S" packet: status report|S-packet]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).
==== R'-packet - soft reset ====
The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPGA_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partner) as well as a reset mask for the on-board chips. Currently the two least significant bits of this byte order reset of the ADC (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage. As with the S-packet at the end of the the hard reset stage, this packet is meant for notification. An explicit query request ([[Ethernet_packets#The query cycle - "Q" packet|Q-packet]]) is recommended for reliable voltage values on board. (Certainly the validity of the highest ADC channel 7 is not guaranteed after an ADC reset request in the R'-packet)
=== The query cycle - "Q" packet ===
=== The query cycle - "Q" packet ===
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Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte. All channels are present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value. The total size of the data in a programming packet is:
Following this are 64 bytes of programming data listing the values for channels 0-31 (in that order) in 2-byte words. Each channel needs 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte. All channels are present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value. The total size of the data in a programming packet is:
== Packets from the FPGA to the PC ==
== Packets from the FPGA to the PC ==