Changes

== Packets from the PC to the FPGA ==

== Packets from the PC to the FPGA ==

We will use six types of packets in our communications, paired into three "conversations" or "cycles": a reset cycle, a query cycle, a programming cycle.  Each packet's data section will begin with a single-byte code to identify the packet type.  As a mnemonic, these bytes will use ASCII codes to represent a single-letter shorthand for each packet.

We will use six types of packets in our communications, paired into three "conversations" or "cycles": a reset cycle, a query cycle, a programming cycle.  Each packet's data section will begin with a two-byte code to identify the relevant board and packet type.  As a mnemonic, these bytes will use ASCII codes to represent a single-letter shorthand for each packet.

The "R group" of packets sent from the PC to the card to initiate a reset process in various forms.  Two possible reset packets (corresponding to two degrees of reset) are possible

The "R group" of packets sent from the PC to the card to initiate a reset process in various forms.  Two possible reset packets (corresponding to two degrees of reset) are possible

* Full or "Hard" reset: This resets all chips on the board. This will contain no data as no further instructions can be remembered after a board reset.

* Full or "Hard" reset: This resets all chips on the board. This will contain no data as no further instructions can be remembered after a board reset.

* Selective or "Soft" reset: This will have flags to reset the Ethernet chip, the ADC/Temperature sensor group (SPI bus), and the DAC.

* Selective or "Soft" reset: This will have flags to reset the ADC and the DAC. A Soft Reset command also finalizes a Hard Reset cycle, as it allows the control board to learn the PC's MAC address. (Subsequent unicast communication makes for a cleaner system compared to an all-broadcast scheme)

===== R-packet - hard reset =====

===== R-packet - hard reset =====

The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPGA_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC) loads its own MAC address and transmits an [[Ethernet_packets#"S" packet: status report|S-packet]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).

The packet type byte (2nd in packet payload) will be an ASCII '''R''': 0x52, 0101 0010. This packet orders control passed to the [[FPGA_Reset|Reset_hard]] module which resets the Ethernet Controller chip (EC), loads its own MAC address and transmits an [[Ethernet_packets#"S" packet: status report|S-packet]] to confirm completion of this stage and allow the PC to pair the source MAC address with the included slot Location address (always in the 1st byte of payload).

===== R'-packet - soft reset =====

===== R'-packet - soft reset =====

The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPGA_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partner) as well as a debug byte and a reset mask for the on-board chips. The syntax of the debug byte has not been defined yet, but the reset mask currently the two least significant bits as reset flags for SPI bus (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage.

The packet type byte (2nd in packet payload) will be a 0xD2, '''1'''101 0010 - essentially an ASCII R with the MSB flipped to '1'. This packet orders a more customized [[FPGA_Reset|"soft" reset]]. After the mandatory Location and Packet Type bytes, this packet carries the 6-byte PC MAC address (to allow the FPGA to record the address of its conversation partner) as well as a reset mask for the on-board chips. Currently the two least significant bits of this byte order reset of the ADC bus (bit 1) and DAC (bit 0). Another [[Ethernet_packets#"S" packet: status report|S-packet]] is returned after this stage.

=== The query cycle - "Q" packet ===

=== The query cycle - "Q" packet ===