Changes

[[Image:Spartan.jpg|right]]

[[Image:Spartan.jpg|right]]

The FPGA is the hub of the digital control board.  All components communicate through the FPGA and are controlled by the FPGA.  The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA.  The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this.  The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic. The code for the FPGA has been written in [[VHDL_tutorial|VHDL]] and is in the final stages of debugging. The question as to which size of FPGA to choose from the available 50k-1400k may be settled, as the current design implementation fits within the 50k unit.  

The FPGA is the hub of the digital control board.  All components communicate through the FPGA and are controlled by the FPGA.  The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA.  The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this.  The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic. The code for the FPGA, written in [[VHDL_tutorial|VHDL]], is complete. Remaining tweaks are subject to the use experience during beam tests and any other field experience.

The code fits within the smallest version of the chip in terms of gates and pins, which greatly simplifies the board assembly and reduces cost. The design did, however rely on Xilinx ''primitives'' (instantiation of device-specific resources) for large registers required by the code.

The data sheet, user guide, configuration guide, and other documentation regarding the FPGA can be downloaded from the [http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Spartan-3A Xilinx website].

The data sheet, user guide, configuration guide, and other documentation regarding the FPGA can be downloaded from the [http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Spartan-3A Xilinx website].

Much of the FPGA programming is concerned with the complex operations of the Ethernet controller chip [[#The Ethernet controller|CP2200/1 discussed below]]. This core interacts with the DAC and SPI (bus for ADC and Temperature sensor) controller modules when access to these chips is required. Please see the relevant pages from the following list.

Much of the FPGA programming is concerned with the complex operations of the Ethernet controller chip [[#The Ethernet controller|CP2200/1 discussed below]]. This core interacts with the DAC and the SPI-based ADC and Temperature sensor when access to these chips is required. Please see the relevant pages from the following list.

* [[Programming the Ethernet controller|Programming the Ethernet controller (core of FPGA design)]]

* [[Programming the Ethernet controller|Programming the Ethernet controller (core of FPGA design)]]

** [[Reset and Initialization]] - discussion of reset/initialization needs of our chips.

** [[Reset and Initialization]] - discussion of reset/initialization needs of our chips.

* [[Programming the DAC|Programming the DAC controller]]

* [[Programming the DAC|Programming the DAC controller]]

=== The Ethernet controller ===

=== The Ethernet controller ===