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SiPM digital control board (view source)
Revision as of 01:04, 5 November 2009
, 01:04, 5 November 2009no edit summary
** [[Reset and Initialization]] - discussion of reset/initialization needs of our chips.
** [[Reset and Initialization]] - discussion of reset/initialization needs of our chips.
* [[Programming the DAC|Programming the DAC controller]]
* [[Programming the DAC|Programming the DAC controller]]
=== The Ethernet controller ===
=== The Ethernet controller ===
After researching a variety of communication buses, including USB, I<sup>2</sup>C, FireWire, and various others, it was decided that the best choice would be Ethernet. Ethernet is based on a multi-layer protocol, with each higher layer adding more advanced capabilities. Only layers one and two are necessary for our purposes, being a local network not connected to a true internet. In addition, due to the wide availability of Ethernet hubs/switches, Ethernet will help to minimize the number of wires that must be run between the control board array and the main computer.
After researching a variety of communication buses, including USB, I<sup>2</sup>C, FireWire, and various others, it was decided that the best choice would be Ethernet. Ethernet is based on a multi-layer protocol, with each higher layer adding more advanced capabilities. Only layers one and two are necessary for our purposes, being a local network not connected to a true internet. The wide availability of Ethernet products is a major advantage of this choice of communication scheme.
We have selected the Silicon Laboratories CP2200/1 Ethernet controller. The two variants of the chip differ (primarily) in packaging and I/O pin count: the CP2201 requires a ''Multiplexed'' Intel Bus interface, saving many pins. The FPGA has been designed around this chip.
We have selected the Silicon Laboratories CP2200/1 Ethernet controller. The two variants of the chip differ (primarily) in packaging and I/O pin count: the CP2201 requires a ''Multiplexed'' Intel Bus interface, saving many pins. The FPGA firmware has been designed around this chip.
The data sheet and other information regarding the Ethernet controller can be downloaded from the [http://www.silabs.com/tgwWebApp/public/web_content/products/Microcontrollers/Interface/en/CP220x.htm Silicon Laboratories website].
The data sheet and other information regarding the Ethernet controller can be downloaded from the [http://www.silabs.com/tgwWebApp/public/web_content/products/Microcontrollers/Interface/en/CP220x.htm Silicon Laboratories website].
=== The DAC ===
=== The DAC ===
The purpose of the control board is to allow remotely programmable bias voltages for the SiPMs. For this purpose a DAC is required. The current design of the tagger microscope calls for 16 SiPMs per electronics card, however designs of up to 24 SiPMs per electronics card are being considered. Various designs were studied, but based on availability of components in the 50V range (DACs and op-amps primarily) the most suitable choice found was the Analog Devices' AD5535. It can go up to 200V with a resolution of 14 bit (roughly 12mV at 200V scale, roughly 3mV at a 50V scale) on 32 channels. As there are so many channels built in to this system, the tagger may be slightly restructured so as to include up to 32 SiPMs per board instead of 16 per board. This DAC defines its own serial interface for communication with the FPGA.
The purpose of the control board is to allow remotely programmable bias voltages for the SiPMs. For this purpose a DAC is required. The current design of the tagger microscope calls for 25 or 30 SiPMs per amplifier board (to read out an entire 5x5 or 5x6 scintillating fiber bundle.) Various designs were studied, but based on availability of components in the 50V range (DACs and op-amps primarily) the most suitable choice found was the Analog Devices' AD5535. It can go up to 200V with a resolution of 14 bit (roughly 12mV at 200V scale, roughly 3mV at a 50V scale) on 32 channels. The chip defines its own serial interface for communication with the FPGA.
The data sheet and other information regarding the DAC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html Analog Devices website].
The data sheet and other information regarding the DAC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html Analog Devices website].
=== The ADC ===
=== The ADC ===
[[Image:SPI-like bus.JPG|thumb|SPI-like bus topology]]
[[Image:SPI-like bus.JPG|thumb|SPI-like bus topology]]
In order to monitor the voltage levels of the power lines and possibly some DAC channels, an ADC is to be included in the design. The Analog Devices' AD7928 is an eight-channel ADC. Based on the selection of components there are six necessary power lines and two necessary grounds, so the AD7928 is capable of monitoring the entire system if need be. It uses a serial protocol that is compatible with the SPI bus to communicate with the FPGA.
In order to monitor the voltage levels of the power lines, an ADC was included in the design. Additional important uses of the chip is monitoring of a DAC channel for online calibration and temperature measurements of the DAC (integrated diode provided) and the amplifier board via its thermistor.
The device chosen is the Analog Devices' AD7928 - an 8-channel ADC. It uses a serial protocol that is compatible with the SPI bus to communicate with the FPGA.
The data sheet and other information regarding the ADC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7928%2C00.html Analog Devices website].
The data sheet and other information regarding the ADC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7928%2C00.html Analog Devices website].
=== Temperature sensor ===
=== Temperature sensor ===
In order to monitor the ambient temperature, a temperature sensor is to be included in the design. The Analog Devices' AD7314 has ten-bit resolution on temperature and is compatible with the SPI bus for communication with the FPGA.
In order to monitor the ambient temperature, a temperature sensor is to be included in the design. The Analog Devices' AD7314 has 10-bit resolution on temperature and is compatible with the SPI bus for communication with the FPGA.
The data sheet and other information regarding the temperature sensor can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html Analog Devices website].
The data sheet and other information regarding the temperature sensor can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html Analog Devices website].