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Digital control board documentation (view source)
Revision as of 21:19, 21 July 2009
, 21:19, 21 July 2009→Pinout Table
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| P40 || CP2201/CS ||
| P40 || CP2201/CS || iCS
| Chip select for ethernet controller
| Chip select for ethernet controller
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|-
| P41
| P41 || CP2201/WR || iWR
| CP2201/WR
| Write enable for ethernet controller
| Write enable for ethernet controller
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|-
| P42
| P42 || DGND ||
| DGND
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|-
| P43
| P43 || CP2201/RD || iRD
| CP2201/RD
| Read enable for ethernet controller
| Read enable for ethernet controller
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|-
| P44
| P44 || CP2201/ALE || ALE
| CP2201/ALE
| Address line enable for ethernet controller
| Address line enable for ethernet controller
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|-
| P45
| P45 || +3.3V ||
| +3.3V
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|-
| P46
| P46 || CP2201/RESET || Eth_iRst
| CP2201/RESET
| Reset pin for ethernet controller
| Reset pin for ethernet controller
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|-
| P47
| P47 || DGND ||
| DGND
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|-
|-
| P48
| P48 || FPGA/INIT_B || [JTAG]
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
| Used during FPGA configuration - see Xilinx documentation
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|-
| P49
| P49 || CP2201/AD0 || AD(0)
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
| Ethernet controller address/data bus, bit 0
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|-
| P50
| P50 || CP2201/AD1 || AD(1)
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
| Ethernet controller address/data bus, bit 1
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|-
| P51
| P51 || FPGA/DIN || [JTAG]
| FPGA/DIN
| Serial data input from EEPROM for configuration
| Serial data input from EEPROM for configuration
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|-
| P52
| P52 || CP2201/AD2 || AD(2)
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
| Ethernet controller address/data bus, bit 2
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| P53
| P53 || FPGA/CCLK || [JTAG]
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at <br>power on to clock the configuration process)<br>See Xilinx documentation
| Configuration clock (signal generated by FPGA at <br>power on to clock the configuration process)<br>See Xilinx documentation
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|-
| P54
| P54 || FPGA/DONE || [JTAG]
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
| Gives configuration status - see Xilinx documentation
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| P55
| P55 || +3.3V ||
| +3.3V
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|-
|-
| P56
| P56 || CP2201/AD3 || AD(3)
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
| Ethernet controller address/data bus, bit 3
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|-
| P57
| P57 || CP2201/AD4 || AD(4)
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
| Ethernet controller address/data bus, bit 4
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|-
| P58
| P58 || DGND ||
| DGND
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| P59
| P59 || CP2201/AD5 || AD(5)
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
| Ethernet controller address/data bus, bit 5
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| P60
| P60 || CP2201/AD6 || AD(6)
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
| Ethernet controller address/date bus, bit 6
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|-
| P61
| P61 || CP2201/AD7 || AD(7)
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
| Ethernet controller address/date bus, bit 7
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|-
| P62
| P62 || No connection ||
| No connection
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|-
| P63
| P63 || DGND ||
| DGND
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|-
| P64
| P64 || No connection ||
| No connection
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| P65
| P65 || No connection ||
| No connection
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|-
| P66
| P66 || +1.2V ||
| +1.2V
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|-
| P67
| P67 || +3.3V ||
| +3.3V
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|-
|-
| P68
| P68 || +3.3V ||
| +3.3V
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|-
|-
| P69
| P69 || DGND ||
| DGND
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|-
|-
| P70
| P70 || ID3 || LocStamp(3)
| ID3
| Backplane location identifier jumper, pins 3 & 4<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 3 & 4<br>Active-low, FPGA should pull high
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|-
| P71
| P71 || ID2 || LocStamp(2)
| ID2
| Backplane location identifier jumper, pins 5 & 6<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 5 & 6<br>Active-low, FPGA should pull high
|-
|-
| P72
| P72 || ID1 || LocStamp(1)
| ID1
| Backplane location identifier jumper, pins 7 & 8<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 7 & 8<br>Active-low, FPGA should pull high
|-
|-
| P73
| P73 || ID0 || LocStamp(0)
| ID0
| Backplane location identifier jumper, pins 9 & 10<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 9 & 10<br>Active-low, FPGA should pull high
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|-
| P74
| P74 || DGND ||
| DGND
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|-
|-
| P75
| P75 || FPGA/TDO || [JTAG]
| FPGA/TDO
| JTAG
| JTAG
|-
|-
| P76
| P76 || FPGA/TCK || [JTAG]
| FPGA/TCK
| JTAG
| JTAG
|-
|-
| P77
| P77 || ID4 || LocStamp(4)
| ID4
| Backplane location identifier jumper, pins 1 & 2<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 1 & 2<br>Active-low, FPGA should pull high
|-
|-
| P78
| P78 || No connection ||
| No connection
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|-
|-
| P79
| P79 || +3.3V ||
| +3.3V
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|-
| P80
| P80 || DGND ||
| DGND
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|-
|-
| P81
| P81 || +1.2V ||
| +1.2V
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|-
| P82
| P82 || No connection || (db) dbShort
| No connection
| Shorts out the waiting timer in FPGA for Ethernet controller initialization (pulled low)
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| P83
| P83 || CLK_5MHZ_2 || DAC_Clk
| CLK_5MHZ_2
| 5 MHz clock output for DAC
| 5 MHz clock output for DAC
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|-
| P84
| P84 || No connection ||
| No connection
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| P85
| P85 || AD5535/DIN || DAC_serData
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
| DAC serial data input (FPGA out -> DAC in)
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|-
| P86
| P86 || No connection ||
| No connection
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| P87
| P87 || DGND ||
| DGND
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| P89
| P88 || AD5535/SYNC || DAC_setISync
| No connection
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| P89 || No connection ||
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| P90
| P90 || No connection ||
| No connection
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|-
|-
| P91
| P91 || DGND ||
| DGND
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|-
| P92
| P92 || +3.3V ||
| +3.3V
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|-
| P93
| P93 || AD7314/CE || SPI_TCE
| AD7314/CE
| Chip enable for temperature sensor
| Chip enable for temperature sensor
|-
|-
| P94
| P94 || (''needs manual connection?''') || SPI_iRst_out
| No connection
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| P95
| P95 || DGND ||
| DGND
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|-
| P96
| P96 || +3.3V ||
| +3.3V
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|-
| P97
| P97 || (former AD7928/DOUT) ||
| AD7928/DOUT
| '''Erroneously wired ADC SPI bus connection'''<br>Connects to DOUT on ADC
| '''Erroneously wired ADC SPI bus connection'''<br>Connects to DOUT on ADC
|-
|-
| P98
| P98 || AD5535/RESET || DAC_iRst
| AD5535/RESET
|Reset pin for DAC
| Reset pin for DAC
|-
|-
| P99
| P99 || DGND ||
| DGND
| PUDC_B pin - enables pullup resistors on user IO and input-only pins during FPGA config.
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| P100
| P100 || FPGA/PROG_B || [JTAG]
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
| Used during FPGA configuration - see Xilinx documentation
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