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SiPM digital control board netlist (view source)
Revision as of 14:55, 24 June 2008
, 14:55, 24 June 2008→FPGA Connections: CLK_OUT connections
|CLK_OUT
|CLK_OUT
|5MHz clock output subdivded from main 20MHz clock
|5MHz clock output subdivded from main 20MHz clock
|Various ICs needing 5MHz clock - see [[#IC netlist|IC netlist]] below
|AD7314 pin 3, AD7928 pin 1, AD5535 pin P9
|----
|----
|ETH_INT
|ETH_INT