Changes

== Byte Fetcher (<tt>getByte</tt>) ==

== Byte Fetcher (<tt>getByte</tt>) ==

Fetches a byte of data from the Ethernet Controller registers via the [FPGA_Transceiver|Transceiver]. This unit creates yet another abstraction layer "in series" with the transceiver. The two step process of sending a request with all accompanying parameters and waiting for reply is now a matter of a single "call". The module does not latch the input data but puts it immediately on the Transceiver control bus. (This is safe since the Transceiver latches the input data and starts the conversation with the EC on the falling edge of its fast clock - a full 25 ns after the rising edge of the "Go" signal sent to <tt>getByte</tt>).

Fetches a byte of data from the Ethernet Controller registers via the [[FPGA_Transceiver|Transceiver]]. This unit creates yet another abstraction layer "in series" with the transceiver. The two step process of sending a request with all accompanying parameters and waiting for reply is now a matter of a single "call". The module does not latch the input data but puts it immediately on the Transceiver control bus. (This is safe since the Transceiver latches the input data and starts the conversation with the EC on the falling edge of its fast clock - a full 25 ns after the rising edge of the "Go" signal sent to <tt>getByte</tt>).

== Write Request (<tt>wrToAddr</tt>) ==

== Write Request (<tt>wrToAddr</tt>) ==

Sends a write request (R/W pin low) to [FPGA_Transceiver|Transceiver] at the specified address with the specified byte of data. The module awaits the "Done" signal from the Transceiver and passes it to the calling module.

Sends a write request (R/W pin low) to [[FPGA_Transceiver|Transceiver]] at the specified address with the specified byte of data. The module awaits the "Done" signal from the Transceiver and passes it to the calling module.

== 2-byte Write Request (<tt>wr2BtoAddr</tt>) ==

== 2-byte Write Request (<tt>wr2BtoAddr</tt>) ==

Coordinates write operations to two adjacent 1-byte registers in the Ethernet Controller chip. This is an essential abstraction because the controller often requires 16-bit exchanges especially when specifying 16-bit locations pointers in random memory access. Only the address of the first register is passed in. Naturally <tt>[[FPGA_Reusables#Write Request (<tt>wrToAddr</tt>)|wrToAddr]]</tt> is used for the individual byte writes.

Coordinates write operations to two adjacent 1-byte registers in the Ethernet Controller chip. This is an essential abstraction because the controller often requires 16-bit exchanges especially when specifying 16-bit locations pointers in random memory access. Only the address of the first register is passed in. Naturally <tt>[[FPGA_Reusables#Write Request (wrToAddr)|wrToAddr]]</tt> is used for the individual byte writes.