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Line 22: + + + − == Auto-reader (<tt>AutoRd</tt>) == − Performs the same function as the Byte Fetcher (described above) but is hard-wired to address the RXAUTORD (0x01). This is convenient because the Ethernet Controller's AutoRead interface will be used extensively to parse through packets. <tt>AutoRd</tt> is in fact just a wrapper around <tt>GetByte</tt> passing through all signals accept the fixed address input.+ + − == Random Access Write (<tt>RAwrToAddr</tt>) == − Writing directly to Ethernet Controller RAM (not to be confused with the control registers) in random access mode requires more work. A 16-bit address needs to be passed in 8 bits at a time to appropriate control registers and the actual 8-bit data is sent on the third transaction. Because the buffer is sometimes loaded in sequentially, this unit is designed to just increment the address of the previous random access write if the passed in address has a '1' in the MSB. (This would never be a legal address, as it is out of range.) The calling module, therefore, does not need to store the current write location of the RAM. <tt>wr2BtoAddr</tt> and <tt>wrToAddr</tt> are very convenient for these three transactions.+ − − − − Because the data values exchanged between the board and the PC range from 10 to 14 bit depth, zero padded 16-bit words will be used. So, to load this 2-byte word into the transfer buffer requires two random access writes. This module packages this functionality by including two calls to <tt>RAwrToAddr</tt> with address increments and input data latching taken into account.+
no edit summary
Fetches a byte of data from the Ethernet Controller registers via the [[FPGA_Transceiver|Transceiver]]. This unit creates yet another abstraction layer "in series" with the transceiver. The two step process of sending a request with all accompanying parameters and waiting for reply is now a matter of a single "call". The module does not latch the input data but puts it immediately on the Transceiver control bus. (This is safe since the Transceiver latches the input data and starts the conversation with the EC on the falling edge of its fast clock - a full 25 ns after the rising edge of the "Go" signal sent to <tt>getByte</tt>).
Fetches a byte of data from the Ethernet Controller registers via the [[FPGA_Transceiver|Transceiver]]. This unit creates yet another abstraction layer "in series" with the transceiver. The two step process of sending a request with all accompanying parameters and waiting for reply is now a matter of a single "call". The module does not latch the input data but puts it immediately on the Transceiver control bus. (This is safe since the Transceiver latches the input data and starts the conversation with the EC on the falling edge of its fast clock - a full 25 ns after the rising edge of the "Go" signal sent to <tt>getByte</tt>).
== Auto-reader (<tt>AutoRd</tt>) ==
Performs the same function as the Byte Fetcher (described above) but is hard-wired to address the RXAUTORD (0x01). This is convenient because the Ethernet Controller's AutoRead interface will be used extensively to parse through packets. <tt>AutoRd</tt> is in fact just a wrapper around <tt>[[FPGA_Reusables#Byte Fetcher (getByte)|getByte]]</tt> passing through all signals accept the fixed address input.
== Random Access Write (<tt>RAwrToAddr</tt>) ==
Writing directly to Ethernet Controller RAM (not to be confused with the control registers) in random access mode requires more work. A 16-bit address needs to be passed in 8 bits at a time to appropriate control registers and the actual 8-bit data is sent on the third transaction. Because the buffer is sometimes loaded in sequentially, this unit is designed to just increment the address of the previous random access write if the passed in address has a '1' in the MSB. (This would never be a legal address, as it is out of range.) The calling module, therefore, does not need to store the current write location of the RAM. <tt>wr2BtoAddr</tt> and <tt>wrToAddr</tt> are very convenient for these three transactions. (The former works well because the 16-bit address registers of the pointer are located contiguously among the EC control registers.)
Note that the module internal memory of the last address used requires that it is instantiated with care. Each instantiation will contain its own internal address register so "opinions on last address" will vary.
== 2-byte Random Access Write (<tt>RAwr2BtoAddr</tt>) ==
Because the data values exchanged between the board and the PC range from 10 to 14 bit depth, zero padded 16-bit words will be used. So, loading a 2-byte word into the transfer buffer requires two random access writes. This module packages this functionality by including two calls to <tt>RAwrToAddr</tt> with address increments and input data latching taken into account.
== Interrupt Catcher <tt>INTCatcher</tt> ==
== 2-byte Random Access Write (<tt>RAwr2BtoAddr</tt>) ==
This is an essential module for listening to interrupts from the EC. There are relevant interrupts in the reset stage and also when awaiting packets. The four possible interrupts for which the FPGA waits (all others are turned off upon post-reset EC configuration) are selected using a 4-bit mask input bus. The interrupt pin of the EC is monitored directly and read operations of the two interrupt registers commence upon the interrupt line going low. If the requested interrupt has in fact occurred a "Done" is returned.