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FPGA Reader
(view source)
Revision as of 20:44, 2 June 2008
1 byte added
,
20:44, 2 June 2008
m
→Ports
Line 27:
Line 27:
* ''state_D'': [out] (3-bit) state register input
* ''state_D'': [out] (3-bit) state register input
* ''state_Q'': [in] (3-bit) state register output
* ''state_Q'': [in] (3-bit) state register output
+
* ''LocStamp'': [in] 8-bit board location value as hard-coded into the board's slot
* ''LocStamp'': [in] 8-bit board location value as hard-coded into the board's slot
Senderovich
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