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FPGA Reader
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Revision as of 20:21, 2 June 2008
13 bytes removed
,
20:21, 2 June 2008
m
→Ports
Line 18:
Line 18:
* ''Clk'': [in] clock
* ''Clk'': [in] clock
−
* ''
/
Rst'': [in] asynchronous
, active-low
reset
+
* ''Rst'': [in] asynchronous reset
Senderovich
1,004
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