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Programming the Ethernet controller (view source)
Revision as of 18:49, 28 October 2007
, 18:49, 28 October 2007→Controller
== Controller ==
== Controller ==
=== Foreword on Timing ===
With a controller this complex, the timing of signals must be inspected even scrupulously than usual. In particular, simultaneous transitions of data and "Done" lines must be avoided. When possible, a one-cycle-delayed "Done" signal is used to ensure that the data lines have been stabilized. (All delays are implemented via the c_delay module which postpones the signal by one cycle via two sequential flip-flops, each shifting by half-cycle). When this is inconvenient (e.g. when writing to registers) the target component must not be enabled on rising edges on "Go" or the clock. The registers, for instance, have been designed to read values on the <i>falling edge</i> of the clock - middle of the "Go" pulse, safely after the data line transitions.
=== Non-State Components ===
=== Non-State Components ===