Changes

=== State interconnect ===

=== State interconnect ===

These states will form the outline of the functional block diagram.  Within each state will be a smaller process or set of processes, possibly broken into substates.  Additionally we will have a central ''state'' register.  Each block reads the state value in the register and enables itself upon seeing its own value.  After completion of its function, a block will write a new value to the state register to enable the next block.

These states will form the outline of the functional block diagram.  Within each state will be a smaller process or set of processes, possibly broken into substates.  This implementation calls for a central ''state'' register.  Each block reads the state value in the register and enables itself upon seeing its own value.  After completion of its function, a block will write a new value to the state register to enable the next block. With several modules writing to the register, usual precautions must be taken to avoid more than one drivers forcing a line simultaneously. All modules must be designed to go to high impedance on their output lines when they are not active.

=== State variable ===

=== State variable ===