461
edits
Changes
Jump to navigation
Jump to search
Line 203:
Line 203: − + Line 239:
Line 239: − + + Line 358:
Line 359: − + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Programming the Ethernet controller (view source)
Revision as of 19:46, 19 July 2007
, 19:46, 19 July 2007no edit summary
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''New_St'': new state to load into state register; tied to 010
*** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high
=== (010) Idle ===
=== (010) Idle ===
** outputs
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
*** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high
=== (011) Read Packet ===
=== (011) Read Packet ===
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; tied to 111
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high
=== (111) Transmit "D" ===
=== (111) Transmit "D" ===
This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.
This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.
inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
blocks
* '''Loader'''
** Loads the DAC values into a packet in the transmission buffer of the CP2200/1. Loops through all values and loads them in order (channel zero to channel thirty-one).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin loading a packet
*** ''TxRx_Done'': ''Done'' signal on transceiver
*** ''Data'': 14-bit data bus from internal registers
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** Tells CP2200/1 to send the packet
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, connected to ''Done'' signal from Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high