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Programming the Ethernet controller (view source)
Revision as of 20:21, 19 July 2007
, 20:21, 19 July 2007no edit summary
*** ''Q'': three-bit data-out bus
*** ''Q'': three-bit data-out bus
* '''temperature register'''
* '''temperature register'''
** A ten-bit register to store the most recent temperature data.
** A 16-bit register to store the most recent temperature data.
** inputs
** inputs
*** ''Clk'': clock
*** ''Clk'': clock
*** ''Q'': ten-bit data-out bus
*** ''Q'': ten-bit data-out bus
* '''ADC registers'''
* '''ADC registers'''
** A set of eight 12-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
** A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
** inputs
** inputs
*** ''Clk'': clock
*** ''Clk'': clock
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
* '''DAC registers'''
* '''DAC registers'''
** A set of 32/24/16 14-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** inputs
** inputs
*** ''Clk'': clock
*** ''Clk'': clock
=== (100) Poll Status ===
=== (100) Poll Status ===
This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.
This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Additionally, it converts all values to 16-bit two's-complement before storing locally. Once all status values have been updated it transitions to state 101.
Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.
Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.
blocks
blocks
* '''ADC Poll'''
* '''ADC Poll'''
** Updates values stored in the FPGA from the ADC.
** Updates values stored in the FPGA from the ADC. Obtains data from ADC, converts to 16-bit two's-complement, and stores.
** inputs
** inputs
*** ''Clk'': clock
*** ''Clk'': clock
*** ''En'': enable line for writing to the internal registers
*** ''En'': enable line for writing to the internal registers
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Data'': 12-bit data bus to carry data to FPGA internal registers
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Temp Poll'''
* '''Temp Poll'''
** Updates value stored in the FPGA from the temperature sensor.
** Updates value stored in the FPGA from the temperature sensor. Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores.
** inputs
** inputs
*** ''Clk'': clock
*** ''Clk'': clock
*** - All temperature sensor control lines -
*** - All temperature sensor control lines -
*** ''En'': enable line for writing to the internal register
*** ''En'': enable line for writing to the internal register
*** ''Data'': 10-bit data bus to carry data to FPGA internal registers
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
* '''Coordinator'''
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.
This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.
inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
blocks
* '''Temp Loader'''
** This block reads the temperature value from the internal registers and loads it to the transmit buffer.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''ADC Loader'''
** This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Temp Loader
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''Sel'': 3-bit select bus for internal registers
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Padder'''
** This block pads the packet to the minimum 46 bytes. Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of ADC Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** This block tells the CP2200/1 to send the completed packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Padder
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
=== (110) Program DAC ===
=== (110) Program DAC ===