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*** - All ADC control lines -
 
*** - All ADC control lines -
 
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
 
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
 +
*** ''En'': enable line for writing to the internal registers
 
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
 
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
 
*** ''Data'': 12-bit data bus to carry data to FPGA internal registers
 
*** ''Data'': 12-bit data bus to carry data to FPGA internal registers
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** outputs
 
** outputs
 
*** - All temperature sensor control lines -
 
*** - All temperature sensor control lines -
 +
*** ''En'': enable line for writing to the internal register
 
*** ''Data'': 10-bit data bus to carry data to FPGA internal registers
 
*** ''Data'': 10-bit data bus to carry data to FPGA internal registers
 
* '''Coordinator'''
 
* '''Coordinator'''
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