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Programming the Ethernet controller (view source)
Revision as of 15:25, 19 July 2007
, 15:25, 19 July 2007no edit summary
:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''
:''See also: [[Ethernet state diagram]]''
== The eight states ==
There are eight major states to the module.
=== State list ===
; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.
=== State interconnect ===
These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.
=== State variable ===
Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S<sub>2:1</sub>:
** S<sub>2</sub> = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S<sub>2:1</sub> = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S<sub>2:1</sub> = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S<sub>2</sub> = 1: "Branch cycles" that execute selectively based on received packets.
*** S<sub>2:1</sub> = 10: "Query cycle" as described in the page on [[Ethernet packets]].
*** S<sub>2:1</sub> = 11: "Programming cycle" as described in the page on [[Ethernet packets]].
* S<sub>0</sub>:
** S<sub>0</sub> = 0: "Setup state" to prepare internal workings for a communication.
** S<sub>0</sub> = 1: "Transfer state" to communicate with the external PC.
== Emulator ==
== Emulator ==