Changes

The VHDL files can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/DAC_VHDL.zip here].

The VHDL files can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/DAC_VHDL.zip here].

== Interface (D) ==

== Interface ==

The AD5535 Digital-to-Analog Converter has a three-wire serial interface and an inverted-logic reset signal.  A serial communication transfers one 19-bit word:

The AD5535 Digital-to-Analog Converter has a three-wire serial interface and an inverted-logic reset signal.  A serial communication transfers one 19-bit word:

The three lines of the interface are ''SYNC'', ''SCLK'', and ''D_in''.  A write to the DAC begins with a falling edge of ''SYNC''.  The next 19 bits (counted off by ''SCLK'') are saved into a shift register  The next transfer begins on another falling edge of ''SYNC'', but transfers do not overlap or interrupt.  A minimum of 200ns is required between exchanges.  ''SCLK'' is ignored except during the 19 shift cycles.  The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically.  In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz.  For further details on timing and protocol, see the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html AD5535 data sheet] supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).

The three lines of the interface are ''SYNC'', ''SCLK'', and ''D_in''.  A write to the DAC begins with a falling edge of ''SYNC''.  The next 19 bits (counted off by ''SCLK'') are saved into a shift register  The next transfer begins on another falling edge of ''SYNC'', but transfers do not overlap or interrupt.  A minimum of 200ns is required between exchanges.  ''SCLK'' is ignored except during the 19 shift cycles.  The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically.  In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz.  For further details on timing and protocol, see the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html AD5535 data sheet] supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).

== Emulator (D) ==

== Emulator ==

[[Image:DAC Emulator Block.JPG|thumb|DAC emulator functional block diagram]]

[[Image:DAC Emulator Block.JPG|thumb|DAC emulator functional block diagram]]

*** ''Q'': 14-bit output bus

*** ''Q'': 14-bit output bus

== Controller (D) ==

== Controller ==

[[Image:DAC Controller Block.JPG|thumb|DAC controller functional block diagram]]

[[Image:DAC Controller Block.JPG|thumb|DAC controller functional block diagram]]