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The VHDL files can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/DAC_VHDL.zip here].
== Interface (D) ==
The AD5535 Digital-to-Analog Converter has a three-wire serial interface and an inverted-logic reset signal. A serial communication transfers one 19-bit word:
{| align="center" cellpadding="1" border="1" cellspacing="1"
|
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
! colspan="5" text-align:left" | A
! colspan="14" text-align:left" | DB
|-
| 04 || 03 || 02 || 01 || 00 || 13 || 12 || 11 || 10 || 09 || 08 || 07 || 06 || 05 || 04 || 03 || 02 || 01 || 00
|}
|}
* A(4:0) is a 5-bit address to select the target DAC channel. A4 is the most-significant bit and transfers first.
* DB(13:0) is a 14-bit voltage code, where <math>V_{out} = 50*V_{RefIn}*\frac{DB(13:0)}{2^{14}}</math>.
** DB = 0 yields V<sub>out</sub> = 0.
** DB = 2<sup>14</sup>-1 (full scale) yields V<sub>out</sub> = 49.9969*V<sub>Ref In</sub>.
The three lines of the interface are ''SYNC'', ''SCLK'', and ''D_in''. A write to the DAC begins with a falling edge of ''SYNC''. The next 19 bits (counted off by ''SCLK'') are saved into a shift register The next transfer begins on another falling edge of ''SYNC'', but transfers do not overlap or interrupt. A minimum of 200ns is required between exchanges. ''SCLK'' is ignored except during the 19 shift cycles. The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically. In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz. For further details on timing and protocol, see the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html AD5535 data sheet] supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).
== Emulator (D) ==
[[Image:DAC Emulator Block.JPG|thumb|DAC emulator functional block diagram]]
The functional block diagram for the emulator is shown to the right. The blocks are:
* '''19-cycle hold'''
** This block takes the single input pulse (one clock cycle wide) and generates a 19-cycle-wide pulse to tell the shift register how long to read in new data. It ignores any additional pulses while the 19-cycle pulse is running. It also enforces a gap of one cycle between serial words.
** inputs
*** ''Reset'': asynchronous, active-low reset
*** ''CLK'': clock
*** ''Begin'': active-low input pulse
** outputs
*** ''Go'': 19-cycle pulse
* '''shift register'''
** This is a serial-in, parallel-out, 19-bit shift register. While the enable line is high it clocks in data. The output is nominally partitioned between address and code, but this is implemented not inside the shift register but by routing the output lines appropriately.
** inputs
*** ''Reset'': asynchronous, active-low reset
*** ''D_in'': data-in serial line
*** ''En'': enable
*** ''Clk'': clock
** outputs
*** ''Addr'': 5-bit parallel address bus
*** ''Code'': 14-bit parallel code bus
* '''follow pulse'''
** This block monitors the enable line generated by the 19-cycle hold block. At the end of the pulse it sees a falling edge and sends a single-cycle pulse to notify the terminal registers that the shift register has loaded a complete word and is ready to write.
** inputs
*** ''Reset'': asynchronous, active-low reset
*** ''Clk'': clock
*** ''D'': 19-cycle input pulse
** outputs
*** ''Q'': single-cycle following pulse
* '''5-to-32 demux'''
** This block is a 5-to-32 demultiplexer. It uses the address generated by the shift register to direct the read-enable pulse from the follow pulse block to the appropriate terminal register.
** inputs
*** ''Select'': 5-bit-wide select bus
*** ''Data'': data line
** outputs
*** ''00:31'': 32 enable lines (on per terminal register)
* '''terminal register''' (x32)
** This is a 14-bit, parallel-in, parallel-out register. There is one terminal register for every channel.
** inputs
*** ''Reset'': asynchronous, active-low reset
*** ''Clk'': clock
*** ''D'': 14-bit data bus
*** ''En'': read enable
** outputs
*** ''Q'': 14-bit output bus
== Controller (D) ==
[[Image:DAC Controller Block.JPG|thumb|DAC controller functional block diagram]]
The functional block diagram for the controller is shown to the right. The blocks are:
* '''19-cycle hold'''
** Identical to the component of the same name in the DAC emulator (see above)
* '''delay'''
** Delays all signals by one clock cycle
** inputs
*** ''Clk'': clock
*** ''D'': signal in
** outputs
*** ''Q'': signal out
* '''shift register'''
** A 19-bit, parallel-in, serial-out shift register. It reads in values every clock cycle that Sh/Rd is low and shifts out values every clock cycle that Sh/Rd is high. The signal is MSB of Addr to LSB of Code.
** inputs
*** ''Clk'': clock
*** ''Reset'': asynchronous, active-low reset
*** ''Addr'': 5-bit address bus
*** ''Code'': 14-bit code bus
*** ''Sh/Ld'': positive-logic shift/negative-logic load
** outputs
*** ''Q'': serial out line
== Interface (D) ==
The AD5535 Digital-to-Analog Converter has a three-wire serial interface and an inverted-logic reset signal. A serial communication transfers one 19-bit word:
{| align="center" cellpadding="1" border="1" cellspacing="1"
|
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
! colspan="5" text-align:left" | A
! colspan="14" text-align:left" | DB
|-
| 04 || 03 || 02 || 01 || 00 || 13 || 12 || 11 || 10 || 09 || 08 || 07 || 06 || 05 || 04 || 03 || 02 || 01 || 00
|}
|}
* A(4:0) is a 5-bit address to select the target DAC channel. A4 is the most-significant bit and transfers first.
* DB(13:0) is a 14-bit voltage code, where <math>V_{out} = 50*V_{RefIn}*\frac{DB(13:0)}{2^{14}}</math>.
** DB = 0 yields V<sub>out</sub> = 0.
** DB = 2<sup>14</sup>-1 (full scale) yields V<sub>out</sub> = 49.9969*V<sub>Ref In</sub>.
The three lines of the interface are ''SYNC'', ''SCLK'', and ''D_in''. A write to the DAC begins with a falling edge of ''SYNC''. The next 19 bits (counted off by ''SCLK'') are saved into a shift register The next transfer begins on another falling edge of ''SYNC'', but transfers do not overlap or interrupt. A minimum of 200ns is required between exchanges. ''SCLK'' is ignored except during the 19 shift cycles. The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically. In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz. For further details on timing and protocol, see the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html AD5535 data sheet] supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).
== Emulator (D) ==
[[Image:DAC Emulator Block.JPG|thumb|DAC emulator functional block diagram]]
The functional block diagram for the emulator is shown to the right. The blocks are:
* '''19-cycle hold'''
** This block takes the single input pulse (one clock cycle wide) and generates a 19-cycle-wide pulse to tell the shift register how long to read in new data. It ignores any additional pulses while the 19-cycle pulse is running. It also enforces a gap of one cycle between serial words.
** inputs
*** ''Reset'': asynchronous, active-low reset
*** ''CLK'': clock
*** ''Begin'': active-low input pulse
** outputs
*** ''Go'': 19-cycle pulse
* '''shift register'''
** This is a serial-in, parallel-out, 19-bit shift register. While the enable line is high it clocks in data. The output is nominally partitioned between address and code, but this is implemented not inside the shift register but by routing the output lines appropriately.
** inputs
*** ''Reset'': asynchronous, active-low reset
*** ''D_in'': data-in serial line
*** ''En'': enable
*** ''Clk'': clock
** outputs
*** ''Addr'': 5-bit parallel address bus
*** ''Code'': 14-bit parallel code bus
* '''follow pulse'''
** This block monitors the enable line generated by the 19-cycle hold block. At the end of the pulse it sees a falling edge and sends a single-cycle pulse to notify the terminal registers that the shift register has loaded a complete word and is ready to write.
** inputs
*** ''Reset'': asynchronous, active-low reset
*** ''Clk'': clock
*** ''D'': 19-cycle input pulse
** outputs
*** ''Q'': single-cycle following pulse
* '''5-to-32 demux'''
** This block is a 5-to-32 demultiplexer. It uses the address generated by the shift register to direct the read-enable pulse from the follow pulse block to the appropriate terminal register.
** inputs
*** ''Select'': 5-bit-wide select bus
*** ''Data'': data line
** outputs
*** ''00:31'': 32 enable lines (on per terminal register)
* '''terminal register''' (x32)
** This is a 14-bit, parallel-in, parallel-out register. There is one terminal register for every channel.
** inputs
*** ''Reset'': asynchronous, active-low reset
*** ''Clk'': clock
*** ''D'': 14-bit data bus
*** ''En'': read enable
** outputs
*** ''Q'': 14-bit output bus
== Controller (D) ==
[[Image:DAC Controller Block.JPG|thumb|DAC controller functional block diagram]]
The functional block diagram for the controller is shown to the right. The blocks are:
* '''19-cycle hold'''
** Identical to the component of the same name in the DAC emulator (see above)
* '''delay'''
** Delays all signals by one clock cycle
** inputs
*** ''Clk'': clock
*** ''D'': signal in
** outputs
*** ''Q'': signal out
* '''shift register'''
** A 19-bit, parallel-in, serial-out shift register. It reads in values every clock cycle that Sh/Rd is low and shifts out values every clock cycle that Sh/Rd is high. The signal is MSB of Addr to LSB of Code.
** inputs
*** ''Clk'': clock
*** ''Reset'': asynchronous, active-low reset
*** ''Addr'': 5-bit address bus
*** ''Code'': 14-bit code bus
*** ''Sh/Ld'': positive-logic shift/negative-logic load
** outputs
*** ''Q'': serial out line