461
edits
Changes
Jump to navigation
Jump to search
mLine 4:
Line 4: − − * Will the PC send a layer-2-only packet? Or will the FPGA need to parse out layers 3 and 4? Line 81:
Line 79: − +
no edit summary
== Open questions ==
== Open questions ==
== Structure of a packet ==
== Structure of a packet ==
| 16 || || 35<sup>*</sup>
| 16 || || 35<sup>*</sup>
|}
|}
Since the minimum number of data bytes in a packet is 46, the packet may need to be padded if only 16 channels are to be used. Padding may not be necessary if the PC includes layer 3 and layer 4 data. Alternately the mask can be eliminated, forcing all channels of the DAC to be reprogrammed every programming cycle; however, having a mask allows a query of all DAC channels: set the mask to all zeros to reprogram nothing and the response will report back channel values according to the FPGA.
Since the minimum number of data bytes in a packet is 46, the packet may need to be padded if only 16 channels are to be used. Alternately the mask can be eliminated, forcing all channels of the DAC to be reprogrammed every programming cycle; however, having a mask allows a query of all DAC channels: set the mask to all zeros to reprogram nothing and the response will report back channel values according to the FPGA.
==== "D" packet: DAC setup complete ====
==== "D" packet: DAC setup complete ====
This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications. The first byte of this packet is an ASCII '''D''': 0x44, 0100 0100. The next 64 (or 48 or 32) bytes are the values of each DAC channel. As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte, channel 31 (or 23 or 15) first, channel 0 last. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC. All channels are reported back, not just those that were reprogrammed during this conversation. This will require that the FPGA (or the RAM in the Ethernet chip) store the values of the DAC channels, as the DAC has no interface to report back the value of a given channel. The size of this packet will be 4 (or 3 or 2) bytes less than for the corresponding programming packet, to account for the programming mask.
This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications. The first byte of this packet is an ASCII '''D''': 0x44, 0100 0100. The next 64 (or 48 or 32) bytes are the values of each DAC channel. As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte, channel 31 (or 23 or 15) first, channel 0 last. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC. All channels are reported back, not just those that were reprogrammed during this conversation. This will require that the FPGA (or the RAM in the Ethernet chip) store the values of the DAC channels, as the DAC has no interface to report back the value of a given channel. The size of this packet will be 4 (or 3 or 2) bytes less than for the corresponding programming packet, to account for the programming mask.